cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 45

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
2.2.6 Scatter/Gather DMA
2.2.7 Interrupts
28237-DSH-001-C
The CN8237’s Direct Memory Access (DMA) coprocessor works in close
conjunction with the segmentation and reassembly coprocessors to gain access to
the PCI bus, transfer the requested data, and notify the segmentation or
reassembly coprocessor that the transfer is complete. The DMA coprocessor
transfers all data using the read and write burst buffers in the PCI Bus Interface.
to the segmentation coprocessor using a gather DMA method. For incoming
messages, the DMA coprocessor moves data from the reassembly coprocessor to
host memory using a scatter DMA method.
not aligned on word boundaries. It also selectively transfers data to comply with
either a big endian or little endian host data structure.
The CN8237 informs the host of segmentation and reassembly activity by means
of maskable interrupts sent to the host processor, triggered by writes to the
segmentation and reassembly status queues.
interrupts at PDU boundaries (called Message Mode), or at data buffer
boundaries (called Streaming Mode).
can be enabled in order to reduce the interrupt processing load on the host. This
has value when the SAR resides in an environment in which the host is not
dedicated to data communications processing.
2.3 Automated Segmentation Engine
The CN8237 can segment up to 64 K VCCs simultaneously. The segmentation
coprocessor block independently segments each channel and multiplexes the
VCCs onto the line with cell level interleaving. For each cell transmission
opportunity, the xBR Traffic Manager tells the segmentation coprocessor which
VCC to send.
NULL adaptation layer, AAL0.
In general, two types of transactions are processed:
• For 32-bit PCI
• For 64-bit PCI
For outgoing messages, the DMA coprocessor moves data from host memory
The DMA coprocessor can handle transfers from the PCI bus with data that is
The user can configure the SAR to generate these status queue entries and
The CN8237 can also be configured with a status queue interrupt delay, which
The CN8237 provides full support of the AAL5 protocol and a transparent or
– 12 or 14 word accesses for data
– 1 to 4 word accesses for control and status messages
– 6 or 7 double word accesses for data
– 1 or 2 double word accesses for control and status messages
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2.3 Automated Segmentation Engine
2.0 Architecture Overview
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