cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 317

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
0x2d8
0x300
0x358
28237-DSH-001-C
31–16
31–16
15–0
15–0
31–8
7–0
Bit
Bit
Bit
—
—
—
AAL5 PDUs Discarded Counter (AAL5_DSC_CNT)
Scheduler Head Tail Register (SCH_HD_TL)
TX_STATUS (TX_STATUS)
Field
Field
Field
Size
Size
Size
16
16
16
16
24
8
Reserved
AAL5_DSC_CNT
SCH_HEAD
SCH_TAIL
Reserved
TX_STAT[7:0]
This register counts the number of AAL5 CPCS-PDUs discarded due to buffer
firewall, buffer underflow, or status overflow. The counter is reset to
assertion of either the HRST* system reset pin or the GLOBAL_RESET bit in the
CONFIG0 register. Optionally, an interrupt can be programmed when the counter
rolls over.
Name
This register indicates the current value of the scheduler priority queue head and
tail pointers. The queue displayed is determined by the value in the SCH_CTRL
(HD_TL_PRI_SEL) register.
Name
This register indicates the status of a PHY device. If the head of line flushing
mechanism is enabled (TX_FIFO_FLUSH_EN set in configuration register 1),
this register indicates if a cell has been discarded due to the head of the line
flushing mechanism. If a bit x of the TX-STAT bitmap is set, PHY x discarded a
cell. If one or more bits of TX_STAT is set, an interrupt is generated (if enabled).
The TX_STAT bitmap is latched until the TX_STATUS register is read by the
host.
Name
Mindspeed Technologies
Not implemented at this time.
AAL5 PDUs discarded by the reassembly coprocessor.
Scheduler Priority Queue Head Pointer.
Scheduler Priority Queue Tail Pointer.
Always set to 0.
Status of TX port x.
™
Description
Description
Description
14.6 Counters and Status Registers
14.0 CN8237 Registers
0
by an
14-27