cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 270

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

12.0 PCI Bus Interface
12.9 Interface Module to Serial EEPROM
12.9.2 Loading the EEPROM Data at Reset
12.9.3 Accessing the EEPROM
12-10
At reset, the PCI Configuration block first reads byte 0x00 of the EEPROM to
determine which fields of the EEPROM should be read. It first looks at the
FIELD_ENABLES bits. If bit 2 is set, it sets bit 20 in the PCI Status register to 0, to
disable Power Management capabilities. It then looks at bits 1 and 0 to see if the
corresponding SVID and/or SID fields are to be loaded into the corresponding PCI
Configuration register fields. If either of these is set to 0, the SUBSYSTEM_ID
and/or SUBSYSTEM_VENDOR_ID fields will default to all 0s.
The EEPROM is accessed through the PCI Configuration space at offset 0x4C,
the EEPROM register. See
register’s contents.
busy). When in this state, the EEPROM can be either written to or read from.
After initiating a read or write operation, the BUSY bit will be a logic 1 (busy)
until the transfer completes. During this time, the application software must poll
the BUSY bit to determine when the transfer has completed. Once completed, the
NO_ACK bit indicates the status of the operation. A logic 1 (no acknowledge)
indicates that no device responded to the request.
BYTE_ADDR and DATA fields and set the READ_WRITE bit to 0. The module
then transfers the data in bits 7:0 (the DATA field) to the device on the bus at the
hardware address at the BYTE_ADDR specified. Application software then polls
the register until the BUSY bit is read as 0 (not busy), which indicates that the
transfer has completed. Software must then check the NO_ACK bit to ensure that
the transaction completed normally. If not, the software should retry the
transaction or signal the error to the user. Since the EEPROM might not respond
until after a few milliseconds after a write transaction, it is recommended that all
operations resulting in NO_ACK=1 be retried several times before issuing the
failure.
register, specifying the BYTE_ADDR to be read and setting the READ_WRITE
bit to 1. The software must then poll the BUSY bit until the operation completes.
At this point the data is returned in the DATA field of the EEPROM register. The
software should check the NO_ACK bit to ensure proper completion of the
transfer with no error.
Before starting an EEPROM operation, the BUSY bit must be a logic 0 (not
To initiate a write operation, the application software must write the
For read operations the application software must also write to the EEPROM
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Section 14.7
for a description of the EEPROM
™
28237-DSH-001-C
CN8237