cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 277

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
13.3.1 UTOPIA Interface
28237-DSH-001-C
In addition to the current UTOPIA level 1 support, this interface provides
complete support for UTOPIA level 2, 8/16 bit mode in both master and slave
modes, including support for multi-PHY in both master and slave modes.
Multi-PHY port shaping is provided by tunnels through one TxFIFO buffer. A
3-bit PORT_ID provides port identification for up to eight ports in master mode
(UTOPIA address 0 through 7) and 32 ports in slave mode, where the SAR is
programmed for one port I.D. The UTOPIA output drives are 8 mA to meet the
multi-PHY specification.
high. In master mode, the PORT_ID field is used as a port identification. On the
segmentation side, the appropriate port identification is written in the PORT_ID
field in the VCC table entry. The maximum allowable PORT_ID is
CONFIG1(NUM_PORTS). On the reassembly side, the UTOPIA interface polls
addresses 0 through CONFIG1(NUM_PORTS) for a cell. When a cell is detected
in a PHY, the cell along with the PORT_ID is transferred to the reassembly block.
An expanded lookup mechanism is used to find the appropriate state table entry.
See
equals CONFIG1(SLAVE_ADDR). In non-multi-PHY master mode,
CONFIG1(SLAVE_ADDR) is output on the RxADDR and TxADDR busses.
64 bytes in single PHY master mode and single/multi-PHY slave mode. On the
reassembly side, the tag is discarded by the UTOPIA interface.
content of all cells including OAM within the VP must be identical.
13.4 UTOPIA Level 2 Interface
The CN8237 supports both UTOPIA Level 1 and Level 2 interfaces. These are
described in general terms below with an emphasis on their differences.
Both Level 1 and Level 2 support odd parity over the width of the data bus.
Multi-PHY mode is enabled by setting CONFIG1(MULTI_PHY) to a logic
In slave mode, the UTOPIA block responds only when the UTOPIA address
Also, routing tag prepending is supported with programmable cell size up to
When F4 PMOAM operation or VP ABR operation is enabled, the routing tag
• UTOPIA Level 1—This is an 8- or 16-bit interface designed for data rates
• UTOPIA Level 2—This interface defines the Multi-port support features
Section 5.2.2.4
up to 200 Mbps at a clock rate of 25 MHz. Both Octet-level and Cell Level
handshaking are supported.
that allow up to 31 UTOPIA devices to multiplex on one UTOPIA bus.
The SAR only supports up to eight PHY devices. It allows either 8- or
16-bit data buses and uses only cell level handshaking. It can transfer up to
800 Mbps when running at 50 MHz in the 16-bit mode.
Mindspeed Technologies
for more details.
™
13.0 ATM UTOPIA Interface
13.4 UTOPIA Level 2 Interface
13-5