cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 265

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
transaction. If any of the following five errors occur, the bus master logic
permanently terminates the transaction, flags an error, and ceases to process any
more commands.
NOTE:
Five possible sources of error are present during any PCI bus master
• Target Abort—The PCI transaction terminates if the addressed target
• Master Abort—If the addressed target does not respond with an
• Parity Error—If the data parity checked during read transfers is
• Interface Disabled—If the driver or application software on the PCI host
• Internal Failure—Upon a synchronization error between the DMA
signals a target abort. In this case, the RTA and MERROR bits in the PCI
Configuration register space are set and the PCI_BUS_STATUS[4] bit in
the SYS_STAT register is set.
HDEVSEL* assertion, then a master abort is flagged. In this case, the
RMA and MERROR bits in the PCI Configuration register space are set,
and the PCI_BUS_STATUS[3] bit in the SYS_STAT register is set.
inconsistent with the state of the HPAR signal, then a parity error is
signaled. In this case, the DPR and MERROR bits in the PCI
Configuration register space are set and the PCI_BUS_STATUS[2] bit in
the SYS_STAT register is set.
CPU has disabled the CN8237 PCI bus master logic (using the M_EN bit
in the Command field of the PCI bus configuration registers), then any
attempt to perform a DMA transaction to the PCI bus results in an error. In
this case, the MERROR and INTF_DIS bits in the PCI configuration space
are set and the PCI_BUS_STATUS[1] bit in the SYS_STAT register is set.
coprocessor and the PCI master logic, an internal failure is flagged. In this
case, the MERROR and INT_FAIL bits in the PCI configuration space are
set, and the PCI_BUS_STATUS[0] bit in the SYS_STAT register is set.
The above errors permanently affect system level operation. Because of
this the system should be re-initialized, since full system level recovery is
unlikely. The bus protocol errors can be cleared either by a software reset
of the associated status flag or flags, that is, RTA, RMA, or DPR, or with a
reset of the PCI bus master logic using the HRST* input pin. For example,
a master abort error can be cleared by writing a logic 1 to the RMA status
bit in the PCI Configuration register space, causing the status bit to be
cleared. Internal failures (attempting to initiate a master transaction with
the interface disabled, or loss of synchronization with the DMA controller)
can only be reset by applying the global reset, CONFIG0
(GLOBAL_RESET), or by asserting the HRST* signal.
Configuration register drives the PCI_BUS_ERROR interrupt. To clear this
interrupt, a logic high must be written to the MERROR bit location. The
MERROR bit can also be cleared by a logic low on the HRST* input pin.
recovering from a PCI master error. The PCI host software can determine
that an error occurred by checking the MERROR bit. It can also determine
if the transaction was a read or write by inspecting the MRD bit, and then
retrieve the read or write address at which an error occurred by reading the
MASTER_READ_ADDR or MASTER_WRITE_ADDR fields.
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Next, the MERROR bit must be cleared. The MERROR bit in the PCI
Several fields are provided in the PCI configuration space to aid in
™
12.4 PCI Bus Master Logic
12.0 PCI Bus Interface
12-5