cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 309

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
0x188
0x1e0
28237-DSH-001-C
31–16
15–0
Bit
31
30
29
Bit
—
—
PCR Queue Interval 2 and 3 Register (PCR_QUE_INT23)
Reassembly Control Register 0 (RSM_CTRL0)
Field
Size
Field
1
1
1
Size
16
16
RSM_ENABLE
RSM_RESET
Reserved
QPCR_INT3
QPCR_INT2
Name
The PCR_QUE_INT23 register fields are used to store the two highest PCR
values used in PCR shaping on priority queues that have been enabled for PCR
shaping by setting the QPCR_ENAx bits in the SCH_PRI register. QPCR_INTx
values are used in order: 3, 2, 1, and 0; highest to lowest. PCR is determined by
1 / (QPCR_INTx
14.5 Reassembly Registers
The Reassembly Control register 0 contains the general control bits for the
reassembly coprocessor. The assertion of the HRST* system reset pin or the
GLOBAL_RESET bit in the CONFIG0 register clears the RSM_ENABLE
control bit.
Name
Mindspeed Technologies
Reassembly enable. Initiates an incoming transfer if set, and halts it if reset.
If this bit is reset while the reassembly coprocessor is running, it temporarily
suspends the activities of the reassembly coprocessor logic. Suspension
takes place on a cell boundary, that is, between the completion of all
processing and transfers required for the current cell, and the start of
processing for the next cell. The hold can be removed and the transfer
resumed by setting the RSM_ENABLE bit. This bit will also be set low
internally on certain reassembly error conditions. This includes parity error
with PHALT_EN. In this case, the error condition should be corrected and
the RSM_ENABLE bit set high to resume operation.
Reassembly reset. Forces a hardware reset of the reassembly coprocessor
when asserted. It must be deasserted before the reassembly coprocessor
will resume normal operation.
Program and read as 0.
The assigned PCR interval, entered as number of schedule table slots,
used to map to the highest priority queue that is enabled for PCR shaping
(using the QPCR_ENAx bits in the SCH_PRI register).
The assigned PCR interval, entered as number of schedule table slots,
used to map to the 2nd-highest priority queue that is enabled for PCR
shaping (using the QPCR_ENAx bits in the SCH_PRI register).
×
SYSCLK_PERIOD
×
™
SLOT_PER).
Description
Description
14.5 Reassembly Registers
14.0 CN8237 Registers
14-19