cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 56

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.8 Standards-Based I/O
2-22
2.8 Standards-Based I/O
PCI Bus I/O
The PCI bus interface implements the full set of address, data, and control signals
required to drive the PCI bus as a master, and contains the logic required to
support arbitration for the PCI bus. This interface is PCI Version 2.1-compliant.
core to connect to a serial EEPROM. This 128-byte EEPROM is used to store
specific PCI configuration information, loaded into the PCI configuration space
at reset. This allows for several user-configurable features:
ATM PHY I/O
The CN8237’s ATM PHY interface communicates with and controls the ATM
link interface device, which carries out all the transmission convergence and PHY
media dependent functions defined by the ATM protocol. Two modes of
operation are provided: standard UTOPIA and slave UTOPIA. Standard UTOPIA
mode conforms to both UTOPIA Level 1 and Level 2 standards for ATM Layer
devices. Slave UTOPIA mode reverses the control direction for use in place of a
PHY on switch fabrics.
The PCI bus interface also includes an interface module that allows the PCI
• User control of the size of the memory block for PCI addresses
• Enabling byte swapping of control words across the PCI bus
• Loading of Subsystem ID and Subsystem Vendor ID
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237