cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 321

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
0x3a0—Host Interrupt Mask Register 0 (HOST_IMASK0)
28237-DSH-001-C
29–24
21–19
15–12
9–4
Bit
31
30
23
22
18
17
16
11
10
3
2
1
0
Field
Size
1
1
6
1
1
3
1
1
1
4
1
1
6
1
1
1
1
EN_GPI
EN_PHY_INTR
Reserved
Reserved
EN_HSTAT1
Reserved
EN_GFC_LINK
EN_RSM_RUN
EN_RSM_HS_WRITE
Reserved
EN_SEG_RUN
EN_SEG_HS_WRITE
Reserved
EN_AAL5_DSC_RLOVR
EN_CELL_DSC_RLOVR
EN_CELL_RCVD_RLOVR
EN_CELL_XMIT_RLOVR
This register contains the interrupt enables that correspond to the status bits in the
HOST_ISTAT0 register. The assertion of the HRST* system reset pin clears all of
the HOST_IMASK0 interrupt enables.
Name
Mindspeed Technologies
Enables interrupt when CPI status is a logic 1.
Enables interrupt when PHY_INTR status is a logic 1.
Set to 0.
Set to 0. Reserved for future status page expansion.
Global interrupt enable for HOST_ISTAT1 status register. Individual
interrupts in HOST_ISTAT1 are enabled in HOST_IMASK1.
Set to 0.
Enables interrupt when GFC_LINK status is a logic 1.
Enables interrupt when RSM_RUN status is a logic 1.
Enables interrupt when RSM_HS_WRITE status is a logic high.
Set to 0.
Enables interrupt when SEG_RUN status is a logic high.
Enables interrupt when SEG_HS_WRITE status is a logic high.
Set to 0.
Enables an interrupt when AAL5_DSC_RLOVR status is a logic high.
Enables an interrupt when CELL_DSC_RLOVR status is a logic high.
Enables an interrupt when CELL_RCVD_RLOVR status is a logic high.
Enables an interrupt when CELL_XMIT_RLOVR status is a logic high.
™
Description
14.6 Counters and Status Registers
14.0 CN8237 Registers
14-31