cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 301

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
0x108
(SEG_VBASE)
0x110
28237-DSH-001-C
31–16
31–16
15–0
15–0
Bit
Bit
—
—
Segmentation VCC Table and Schedule Table Base Address Register
Segmentation PM Base Register (SEG_PMBASE)
Field
Field
Size
Size
16
16
16
16
SEG_SCHB[15:0]
SEG_VCCB[15:0]
SEG_BCKB[15:0]
SEG_PMB[15:0]
The SEG_VBASE register sets the base address in SAR SEG-shared memory for
the segmentation VCC table and the schedule table. Both base addresses are
128-byte aligned, and only the 16 most significant bits of the address are
specified in the SEG_VBASE register.
NOTE:
The SEG_PMBASE register sets the base address in SAR SEG-shared memory
for the VBR bucket table and the performance monitoring table. Both base
addresses are 128-byte aligned, and only the 16 most significant bits of the
address are specified in the SEG_PMBASE register.
NOTE:
Name
Name
The PCI address of these structures is (REGISTER_VALUE
SEG_MEMORY_BASE_ADDRESS.
The PCI address of these structures is (REGISTER_VALUE
SEG_MEMORY_BASE_ADDRESS.
Mindspeed Technologies
Base address for the schedule table.
Base address for the segmentation VCC table.
Base address for the VBR bucket table. (See
loading bucket table entries.)
Base address for the performance monitoring table.
™
Description
Description
Section
14.3 Segmentation Registers
14.0 CN8237 Registers
6.2.4.4, for details on
×
×
0x80) +
0x80) +
14-11