cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 286

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

13.0 ATM UTOPIA Interface
13.8 Loopback Mode
Figure 13-7. Transmit Timing in Slave UTOPIA Level 1 Mode
13-14
TXD/TXPAR
(TXFLAG*)
(TXMARK)
NOTE(S):
(1)
(2)
(3)
(4)
TXCLAV
TXSOC
TXCLK
TXEN*
TXCLAV goes active when a complete cell is in the transmit FIFO buffer.
Example of physical device deactivating TXEN*.
The TXD/TXPAR and TXSOC lines are three-stated (floated) when TXEN* is sampled high (de-asserted).
Physical device can keep TXEN* active while TXCLAV is inactive.
(1)
H1
TxEN* is sampled asserted. Simultaneously, the odd parity computed over the
TxDATA[15:0] lines is driven onto the TxPar output. The TxSOC (TxMARK)
line is driven by the SAR to indicate start of cell. If the TxCLAV (TxFLAG*)
output is asserted by the CN8237, the transmit FIFO buffer does not contain a
complete cell. See
13.8 Loopback Mode
The ATM UTOPIA interface can be internally looped by setting the FR_LOOP
bit in the CONFIG1 register to a logic high. This mode uses the internal system
clock for operation; therefore, a framer clock is not needed during loopback
operation.
control signals, so the path from the segmentation coprocessor to the reassembly
coprocessor can be tested. The internal connections of the ATM interface signals
are connected, as
UTOPIA Mode and the receive side is put into the Reverse UTOPIA Mode.
TxEN*, and RxCLAV (RxFLAG*) are three-stated, so there are no output
conflicts with other devices connected to these signals.
NOTE:
Transmit data is driven on TxDATA[15:0] on the rising edge of TxCLK after
When the FR_LOOP signal equals 1, the interface loops back the data and
In this mode, the outputs of the chip, TxDATA, TxPAR, TxSOC (TxMARK),
***
A reset of the reassembly coprocessor is required after changing the
FR_LOOP bit, because this changes the source of the clock to the ATM
UTOPIA interface circuitry. To accomplish this reset, assert RSM_CTRL0
(RSM_RESET).
Mindspeed Technologies
H5
Figure 13-8
P1
Figure
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
P2
(2)
13-7.
illustrates. The transmit side is put into the
(3)
(3)
P3
™
***
P48
(4)
28237-DSH-001-C
H1
H2
CN8237
8237_101