cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 346

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

15.0 SAR Initialization—Example Tables
15.4 General Initialization
15.4.1 General Control Registers
Table 15-9. Table of Values for General Control Register Initialization (1 of 3)
15-14
CONFIG0
(Configuration Register 0)
Register
15.4 General Initialization
Before the SAR is enabled, the host must allocate and initialize all of the general
SAR control registers.
GLOBAL_RESET
PCI_MSTR_RESET
PCI_ERR_RESET
INT_LBANK
MEMTYPE
MEMCTRL
BANKSIZE[2:0]
NUMBANKS[1:0]
PCI_READ_MULTI
PCI_ARB
ENDIAN
FORCE64
STATMODE
DIVIDER
Reserved
Mindspeed Technologies
Field
Table 15-9
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Initialized
Value
0 – 1
1–0
100
0x0
0x0
0x0
10
01
0
0
0
0
1
1
1
lists the initialized values for each field.
™
This must be toggled to a logic high and
back to a logic low after completion of all
initialization, but before RSM and SEG
coprocessors are enabled.
Use GLOBAL_RESET to reset SAR.
Must be initialized to 0.
Should be set to 0 during initialization, but
set to 1 after system reset.
Selects zbt memory.
Selects 0 wait state SRC shared memory.
Selects 1 MB memory bank.
For both RSM and SEG.
PCI Read Multiple Command used.
Round-robin arbitration of internal
read/write PCI master.
Big Endian mode selected.
PCI master will always perform 64-bit
transfers
Selects BOM sync hardware mode.
Divide by 128 selected for CLOCK prescaler.
Must be initialized to 0.
Notes
28237-DSH-001-C
CN8237