cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 320

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

14.0 CN8237 Registers
14.6 Counters and Status Registers
0x388—Host Processor Interrupt Status Register 1 (HOST_ISTAT1)
14-30
NOTE(S):
1. L = Level-sensitive status—A logic 1 on the status bit causes an interrupt when enabled by the corresponding IMASK bit.
2. E = Event driven status—A 0 > 1 transition on the status bit causes an interrupt when enabled. Reading the status register
3. D = Dual Event status—A 0 > 1 and 1 > 0 transition on the status bit can be enabled to cause an interrupt. Reading the status
4. Only host reads reset the status bits in the HOST_ISTAT0 register.
28–27
23–16
10–3
Bit
31
30
29
26
25
24
15
14
13
12
11
2
1
0
Reading the status does not clear the status or interrupt. The source of the condition causing the status must be cleared
before the status or interrupt is cleared.
clears the status bit and the interrupt.
register clears the status bit and the interrupt.
Field
Size
1
1
1
2
1
1
1
8
1
1
1
1
1
8
1
1
1
Type
—
—
—
—
—
L
L
E
E
E
E
E
E
E
E
E
E
(1)
PCI_BUS_EROR
Reserved
TX_DISCARD
Reserved
DMA_AFULL
FR_PAR_ERR
FR_SYNC_ERR
Reserved
RS_QUEUE_FULL
RSM_OVFL
RSM_HS_FULL
Reserved
RSM_HF_EMPT
Reserved
SEG_UNFL
SEG_HS_FULL
Reserved
Mindspeed Technologies
Name
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
This bit is set if the MERROR bit in the PCI configuration
register is set. The MERROR bit is reset by either writing a
logic 1 to the MERROR bit in the PCI configuration register,
or setting the CONFIG0(PCI_ERR_RESET) bit to a logic
high.
Read as 0.
Set when any bit in TX_STATUS is a logic 1. TX_DISCARD is
reset to 0 after the Host reads the TX_STATUS register.
Read as 0.
Set when the incoming DMA burst FIFO becomes almost
full.
Set on the occurrence of a parity error on the reassembly
ATM physical interface.
Set on the occurrence of a synchronization error on the
reassembly ATM physical interface.
Read as 0.
Reassembly/segmentation queue full condition.
Reassembly overflow. Indicates that a cell was lost due to a
FIFO buffer full condition.
Set on the occurrence of a host status queue full condition.
Read as 0.
Set on the occurrence of a host free buffer queue empty
condition.
Read as 0.
Segmentation underflow indicates that a scheduled cell
could not be sent due to lack of PCI bandwidth.
Indicates that the segmentation host status queue is full.
Read as 0.
™
Description
28237-DSH-001-C
CN8237