cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 74

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.3 Write-only Control and Status
Figure 3-2. Peer-to-Peer vs. Centralized Memory Data Transfers
3-4
Frame I/O
Peer
PCI
PCI Card
Memory
Peer
Figure 3-2
buffers require store-forward operations, while the peer buffers enable
peer-to-peer transfers. Thus, peer-to-peer transfers reduce the use of the PCI bus.
3.3 Write-only Control and Status
For host-based applications, the host manages the CN8237 SAR using write-only
control and status queues. This architecture minimizes PCI bus use by eliminating
reads from the control path. PCI writes use the bus much more efficiently than
PCI reads. During a PCI write, the target can post the write data in an internal
FIFO buffer, terminate the transaction, and immediately release the bus. On the
other hand, during reads, the target retrieves the data while holding the bus. Since
the data retrieval takes some time, reads increase the PCI bus utilization.
(PDU) fetches. All control and status transactions are writes. This section
describes the management of write-only queues. The purpose and entries of each
class of queue are described in later chapters.
Table 3-1. CN8237 Control and Status Queues
The CN8237’s write-only architecture uses reads only for segmentation data
Table 3-1
Frame I/O
Host
Control
PCI
Status
Type
PCI Motherboard
Mindspeed Technologies
PCI BUS
shows the difference between these two options. Centralized memory
defines the CN8237 control and status queues.
2
Centralized
1
Memory
Segmentation status queue
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
Transmit queue
Segmentation
1
LEGEND:
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CN8237
PCI Transaction
Peer-to-Peer Transaction
Centralized Memory Transaction
Data Buffer
Reassembly status queue
Free buffer queue
Reassembly
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