cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 315

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
0x228
0x230
28237-DSH-001-C
31–16
31–24
15–0
7–0
Bit
Bit
—
—
TX_FIFO_CTRL (TX_FIFO_CTRL)
TX_PORT_CTRL (TX_PORT_CTRL)
Field
Field
Size
Size
16
16
24
8
Reserved
TX_CNTR
Reserved
TX_PORT_DIS
The TX_FIFO_CTRL register sets a counter compare value that is used for the
head of line flushing mechanism of the transmit FIFO. If head of line flushing is
enabled in configuration register 1, a counter is reset when the UTOPIA master in
multi-PHY mode puts out the address of a PHY device, and the counter is
increased based on UTOPIA TX_CLK. Once the counter reaches the TX_CNTR
value and no UTOPIA CLAV signal has been received from the PHY device, the
cell in the FIFO is discarded.
NOTE:
This register disables UTOPIA ports, if the TX_FIFO_FLUSH_EN bit in
configuration register 1 is set. If bit x of the TX_PORT_DIS bitmap is set, cells
belonging to PHY x are being discarded.
NOTE:
Name
Name
TX_CNTR must not have a value of
mechanism is enabled.
No TX_STATUS bit is set.
Mindspeed Technologies
Always set to 0.
Always set to 0.
Counter values for TX_FIFO flush mechanism.
Disables PHY port x.
™
Description
Description
0
, if the head of the line flushing
14.5 Reassembly Registers
14.0 CN8237 Registers
14-25