cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 228

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

8.0 DMA Coprocessor
8.4 Master Transactions
8.4.1 Data Transfers
8.4.2 Control Word Transfers
8.5.1 Control Word Transfers
8-2
8.4 Master Transactions
The SAR supports both big endian and little endian processors in the PCI address
space. Bit 15 (ENDIAN) in SRC Configuration Register 0 controls all data byte
swapping. Bit 30 (MSTR_CTRL_SWAP) in the Special Status Register (PCI
Config Address 0x40) controls all control byte swapping. Bit 27
(MSTR_DATA_DWORD) in the Special Status Register (PCI Config Address
0x40) controls Data Dword Conversion. Bit 26 (MSTR_CTRL_DWORD) in the
Special Status Register (PCI Config Address 0x40) controls the Control Dword
Conversion.
conversion. Dword Conversion is used to determine which 32-bit word is placed
on the PCI Bus first during a 32-bit transaction. Data transfers do not have to be
byte aligned.
The SAR internally distinguishes between data and control transactions. The SAR
performs byte swapping based on bit 30 (MSTR_CTRL_SWAP) in the Special
Status Register (PCI Config Address 0x40). The SAR performs Dword
Conversion based on bit 26 (MSTR_CTRL_DWORD) in the Special Status
Register (PCI Config Address 0x40). This allows the order of the 32-bit words to
be swapped. Control word transfers are byte aligned.
segmentation status queue writes, read update pointer writes, and reassembly
buffer descriptor next pointers.
8.5 Slave Transactions
All slave transactions consist of control words. There are two types of control
word manipulation that can take place on slave transactions: Byte swapping and
Quadword (64-bit) to Dword (32-bit) Conversion.
The SAR accepts 64-bit or 32-bit data as a slave. Since the Local Memory is
32 bits, a 64-bit access is converted to two 32 accesses. Under programmable
control by bit 28 (SLAVE_DWORD) in the PCI Special Status Register (PCI
Config Address 0x40), either bits [31:0] or bits [63:32] are mapped to address
0x00. Dword Conversion is performed on 64-bit transfers only.
The SAR can perform a full matrix of byte lane swapping and Dword
Control transfers include the following data structures: reassembly and
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237