cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 249

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
28237-DSH-001-C
10.2 Memory Bank Characteristics
The external memory is organized in one to four banks of up to 4 MB each (8 MB
future). The system can use any number of banks to fulfill the memory
requirements; the only stipulation is that the banks must be of the same size and
organization. BANKSIZE[2:0] (bits 23–21) in the CONFIG0 register denotes the
size of the memory banks and allows the CN8237 to incorporate the various bank
sizes into contiguous memory.
BANKSIZE[2:0] control bits.
Table 10-3. BANKSIZE Selection Number
synchronous SRAM. The local memory interface consists of one SEG and one
RSM coprocessor. Each port is 32 bits wide and operates up to 66 MHz. Each
coprocessor is able to address up to 4 MB (8 MB future expansion) of either ZBT
or syncburst synchronous SRAM. For syncburst SRAM, the RBW[3:0]* and
SBW[3:0]* outputs become byte enables for both reads and writes. When reading
local memory, entire 32-bit words are always read.
bank using by_16 RAM. To connect different sized RAM banks, simply use more
or less address bits; all other control remains the same.
NOTE:
(CONFIG0)
BANKSIZE
The memory controller is designed to work with either ZBT or syncburst
111
110
101
100
011
010
001
000
The number and type of ZBT or syncburst synchronous SRAM chips used
affect the address and data bus capacitance and, therefore, the AC timing
specifications and the required ZBT or syncburst synchronous SRAM
speed. The use of by_16 devices causes more address bus loading than the
use of by_32 devices. See
Mindspeed Technologies
Bank Memory
Organization
512 k × 32
256 k × 32
128 k × 32
64 k × 32
32 k × 32
Reserved
2M × 32
1M × 32
Table 10-3
Chapter 16.0
Total Bank Size
(Bytes)
512 k
256 k
128 k
8 M
4 M
2 M
1 M
—
™
gives the coding of the
for detailed timing information.
Future expansion
Two 1 M × 16, one 1 M × 32
Two 512 k × 16, one 512 k x 32
Two 256 k × 16, one 256 k x 32
One 128 k × 32, two 128 k × 16
One 64 k × 32, two 64 k × 16
One 32 k × 32
Figure 10-1
10.2 Memory Bank Characteristics
10.0 Local Memory Interface
Typical Implementation
shows a typical
—
10-3