cn8237 Mindspeed Technologies, cn8237 Datasheet - Page 128

• Manufacturer Part Number: cn8237
• Description: Atm Oc-12 Servicesar Plus With Xbr Traffic Management
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.4 Buffer Management
5.4.7.5 DMA FIFO Buffer
5-20
5.4.7.6 Error Conditions
Full
The purpose of this function is to allow a graceful recovery from an incoming
DMA FIFO buffer full condition. Without this function, the reassembly
coprocessor is stalled when the FIFO buffer is full until recovery from the full
condition. This causes the cells to be dropped indiscriminately on the upstream
side of the reassembly block without any record of which VCCs the cells
belonged to. Upon recovery from the full condition, cells belonging to corrupted
PDUs continue to be processed, which wastes PCI bandwidth during the recovery
phase. This function provides for a more efficient use of host and SAR resources
by allowing the reassembly block to process and drop cells during the full
condition.
condition for subsequent early packet discard. Upon recovery from the full
condition, the reassembly block performs early packet discard on the appropriate
channels as cells are received on those channels. In addition, cells continue to be
dropped on each channel until after an EOM cell is received for that channel.
Early packet discard processing is delayed until recovery from the full condition,
since the status entry also requires the use of the incoming DMA FIFO buffer.
logic high.
(OAM_FF_DSC) should be set to a logic high.
FFPD bit in the RSM status queue entry being a logic high.
NOTE:
Partially reassembled CPCS-PDUs will be recovered for the following error
conditions:
The reassembly block marks all channels that receive a cell during the full
This function is enabled by setting the FF_DSC bit in each VCC entry to a
Similarly, if RSM_CTRL1(OAM_QU_EN) is a logic high, RSM_CTRL1
Early packet discard due to a FIFO buffer full condition is indicated by the
• Non-EOM Max PDU Length exceeded
• Free buffer queue underflow
• Status queue overflow
Avoid having the Status Queue Overflow (or Full Condition) and DMA
FIFO Buffer Full conditions at the same time.
Mindspeed Technologies
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
™
28237-DSH-001-C
CN8237