attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 99
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attiny167-esxz
Manufacturer Part Number
attiny167-esxz
Description
8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY167-ESXZ.pdf
(277 pages)
- Current page: 99 of 277
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10.11.3
10.11.4
10.11.5
7728A–AUTO–07/08
Timer/Counter0 Register – TCNT0
Output Compare Register A – OCR0A
Asynchronous Status Register – ASSR
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
10-5.
Table 10-5.
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Register.
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
• Bit 7 – Res: Reserved Bit
This bit is reserved in the ATtiny167 and will always read as zero.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input
buffer is enabled and an external clock can be input on XTAL1 pin instead of an external crystal.
Writing to EXCLK should be done before asynchronous operation is selected. Note that the
crystal oscillator will only run when this bit is zero.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CS02
0
0
0
0
1
1
1
1
Clock Select Bit Description
OCR0A7
TCNT07
R
7
–
0
R/W
R/W
7
0
7
0
CS01
0
0
1
1
0
0
1
1
EXCLK
OCR0A6
R/W
TCNT06
6
0
R/W
R/W
6
0
6
0
CS00
OCR0A5
TCNT05
AS0
R/W
5
0
R/W
R/W
0
1
0
1
0
1
0
1
5
0
5
0
TCN0UB
OCR0A4
TCNT04
R
4
0
R/W
R/W
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
clk
clk
4
0
4
0
T0S
T0S
T0S
T0S
T0S
T
T
0
0
S
S
/256 (From prescaler)
/1024 (From prescaler)
/8 (From prescaler)
/32 (From prescaler)
/64 (From prescaler)
/128 (From prescaler)
(No prescaling)
OCR0AUB
OCR0A3
TCNT03
R/W
R/W
R
3
0
3
0
3
0
OCR0A2
TCNT02
R/W
R/W
2
0
2
0
R
2
–
0
Description
TCR0AUB
OCR0A1
TCNT01
R/W
R/W
1
0
1
0
R
1
0
ATtiny167
OCR0A0
TCNT00
TCR0BUB
R/W
R/W
0
0
0
0
R
0
0
OCR0A
TCNT0
ASSR
Table
99
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