attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 103

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

11.2
11.2.1
7728A–AUTO–07/08
Timer/Counter1 Prescalers Register Description
General Timer/Counter Control Register – GTCCR
Enabling and disabling of the clock input must be done when T1 has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 11-2. Prescaler for Timer/Counter1
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR0 and PSR1 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR0 and PSR1 bits are cleared by hardware, and
the Timer/Counters start counting simultaneously.
• Bit 0 – PSR1: Prescaler Reset Timer/Counter1
When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared immedi-
ately by hardware, except if the TSM bit is set.
Bit
Read/Write
Initial Value
1. The synchronization logic on the input pin (
CLK
TSM
PSRn
R
7
0
Tn
I/O
Synchronization
ExtClk
6
–
R
0
< f
clk_I/O
R
5
–
0
CSn0
CSn1
CSn2
/2) given a 50/50 % duty cycle. Since the edge detector
Clear
(1)
R
4
–
0
TIMER/COUNTERn CLOCK SOURCE
T1)
0
10-BIT T/C PRESCALER
is shown in
R
3
–
0
clk
Tn
R
2
–
0
Figure
11-1.
PSR0
R/W
1
0
ATtiny167
PSR1
R/W
clk_I/O
0
0
/2.5.
GTCCR
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