attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 210

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

20.2.1
210
ATtiny167
Store Program Memory Control and Status Register – SPMCSR
The Store Program Memory Control and Status Register contains the control bits needed to
control the Boot Loader operations.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny167 and will always read as zero.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATtiny167.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register.
the Signature Row from Software” on page 212.
after SIGRD and SPMEN are set will have no effect.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,
will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-
tion register.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit
will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes Page Erase. The page address is taken from the high part of the Zpointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,
or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire
Page Write operation.
• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a
special meaning, see description above. If only SPMEN is written, the following SPM instruction
will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB
Bit
Read/Write
Initial Value
See ”Reading the Fuse and Lock Bits from Software” on page 211.
R
7
–
0
RWWSB
R
6
0
SIGRD
R
5
0
CTPB
R/W
4
0
for details. An SPM instruction within four cycles
RFLB
R/W
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
SPMEN
R/W
0
0
for details.
7728A–AUTO–07/08
See ”Reading
SPMCSR