attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 94

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

10.9
94
Asynchronous Operation of Timer/Counter0
ATtiny167
Figure 10-11
Figure 10-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
When Timer/Counter0 operates asynchronously, some considerations must be taken.
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Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter0, the timer registers TCNT0, OCR0A, and TCCR0A might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter0 interrupts by clearing OCIE0A and TOIE0.
b. Select clock source by setting AS0 and EXCLK as appropriate.
c. Write new values to TCNT0, OCR0A, and TCCR0A.
d. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.
e. Clear the Timer/Counter0 interrupt flags.
f.
If an 32.768 kHz watch crystal is used, the CPU main clock frequency must be more than
four times the Oscillator or external clock frequency.
When writing to one of the registers TCNT0, OCR0A, or TCCR0A, the value is transferred to
a temporary register, and latched after two positive edges on TOSC1. The user should not
write a new value before the contents of the temporary register have been transferred to its
destination. Each of the three mentioned registers have their individual temporary register,
which means that e.g. writing to TCNT0 does not disturb an OCR0A write in progress. To
detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented.
When entering Power-save mode after having written to TCNT0, OCR0A, or TCCR0A, the
user must wait until the written register has been updated if Timer/Counter0 is used to wake
up the device. Otherwise, the MCU will enter sleep mode before the changes are effective.
This is particularly important if the Output Compare0 interrupt is used to wake up the device,
since the Output Compare function is disabled during writing to OCR0A or TCNT0. If the
write cycle is not finished, and the MCU enters sleep mode before the OCR0UB bit returns
to zero, the device will never receive a compare match interrupt, and the MCU will not wake
up.
If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must
be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TCNTn
(clk
OCRnx
(CTC)
OCFnx
clk
clk
I/O
I/O
Tn
/8)
Enable interrupts, if needed.
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
caler (f
clk_I/O
TOP - 1
/8)
TOP
TOP
BOTTOM
BOTTOM + 1
7728A–AUTO–07/08