attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 100

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

10.11.6
100
ATtiny167
Timer/Counter
0
• Bit 5 – AS0: Asynchronous Timer/Counter0
When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the
Timer/Counter0 acts as a synchronous peripheral.
When AS0 is written to one, Timer/Counter0 is clocked from the low-frequency crystal oscillator
(See ”Low-frequency Crystal Oscillator” on page
”External Clock” on page
the contents of TCNT0, OCR0A, and TCCR0A might be corrupted.
AS0 also acts as a flag: Timer/Counter0 is clocked from the low-frequency crystal or from exter-
nal clock ONLY IF the calibrated internal RC oscillator or the internal watchdog oscillator is used
to drive the system clock. After setting AS0, if the switching is available, AS0 remains to 1, else
it is forced to 0.
• Bit 4 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.
When TCNT0 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new value.
• Bit 3 – OCR0AUB: Output Compare 0 Register A Update Busy
When Timer/Counter0 operates asynchronously and OCR0A is written, this bit becomes set.
When OCR0A has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR0A is ready to be updated with a new value.
• Bit 2 – Res: Reserved Bit
This bit is reserved in the ATtiny167 and will always read as zero.
• Bit 1 – TCR0AUB: Timer/Counter0 Control Register A Update Busy
When Timer/Counter0 operates asynchronously and TCCR0A is written, this bit becomes set.
When TCCR0A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR0A is ready to be updated with a new
value.
• Bit 0 – TCR0BUB: Timer/Counter0 Control Register B Update Busy
When Timer/Counter0 operates asynchronously and TCCR0B is written, this bit becomes set.
When TCCR0B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR0B is ready to be updated with a new
value.
If a write is performed to any of the four Timer/Counter0 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When
reading TCNT0, the actual timer value is read. When reading OCR0A, TCCR0A or TCCR0B the
value in the temporary storage register is read.
Bit
Read/Write
Initial Value
Interrupt Mask Register – TIMSK0
R
7
–
0
29.) depending on EXCLK setting. When the value of AS0 is changed,
R
6
–
0
R
5
–
0
R
4
–
0
28.) or from external clock on XTAL1 pin
R
3
–
0
R
2
–
0
OCIE0A
R/W
1
0
TOIE0
R/W
0
0
7728A–AUTO–07/08
TIMSK0
(See