attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 67

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

9.2.5
7728A–AUTO–07/08
Reading the Pin Value
Table 9-1
Table 9-1.
Note:
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay.
diagram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
Figure 9-4.
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As
indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be
delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
DDxn
0
0
0
1
1
1. Or port-wise PUDx bit in PORTCR register.
summarizes the control signals for the pin value.
PORTxn
Figure
INSTRUCTIONS
Port Pin Configurations
0
1
1
0
1
Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
SYNC LATCH
9-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of
PINxn
(in MCUCR)
r17
PUD
X
X
X
0
1
Figure
(1)
XXX
Output
Output
Input
Input
Input
I/O
9-2, the PINxn Register bit and the preceding latch
pd,max
t
pd, max
Pull-up
and t
0x00
Yes
No
No
No
No
XXX
pd,min
t
pd, min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
respectively.
in r17, PINx
Figure 9-4
ATtiny167
0xFF
shows a timing
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