attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 185

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

17.4
7728A–AUTO–07/08
Starting a Conversion
The voltage reference for the ADC may be selected by writing to the REFS[1..0] bits in ADMUX
and AREFEN bit in AMISCR. The AVcc supply, the AREF pin or an internal 1.1V / 2.56V voltage
reference may be selected as the ADC voltage reference.
The analog input channel and differential gain are selected by writing to the MUX[4..0] bits in
ADMUX register. Any of the 11 ADC input pins ADC[10..0] can be selected as single ended
inputs to the ADC. The positive and negative inputs to the differential gain amplifier are
described in
If differential channels are selected, the differential gain stage amplifies the voltage difference
between the selected input pair by the selected gain factor 8x or 20x, according to the setting of
the MUX[4..0] bits in ADMUX register. This amplified value then becomes the analog input to the
ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
The on-chip temperature sensor is selected by writing the code defined in
MUX[4..0] bits in ADMUX register when its dedicated ADC channel is used as an ADC input.
A specific ADC channel (defined in
of an external resistance flowing by a current driving by the Internal Current Source (ISRC).
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA register. Voltage refer-
ence and input channel selections will not go into effect until ADEN is set. The ADC does not
consume power when ADEN is cleared, so it is recommended to switch off the ADC before
entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX register.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data
registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is
blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will
trigger even if the result is lost.
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is in
progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA register. The trigger
source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB register (see
description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the
selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a
method of starting conversions at fixed intervals. If the trigger signal still is set when the conver-
sion completes, a new conversion will not be started. If another positive edge occurs on the
trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set
Table
17-5.
Table
17-5) is used to measure the voltage to the boundaries
ATtiny167
Table 17-5
to the
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