attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 129

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

12.11.3
12.11.4
7728A–AUTO–07/08
Timer/Counter1 Control Register C – TCCR1C
Timer/Counter1 Control Register D – TCCR1D
The three Clock Select bits select the clock source to be used by the Timer/Counter, see
12-11
Table 12-5.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1nx output is changed according to its COM1A/B1:0 and OC1nx bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1A/B1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bit 7:4 – OC1Bi: Output Compare Pin Enable for Channel B
The OC1Bi bits enable the Output Compare pins of Channel B as shown in
116.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CS12
0
0
0
0
1
1
1
1
and
Figure
CS11
0
0
1
1
0
0
1
1
Clock Select Bit Description
OC
FOC
R/W
R/W
1
7
0
7
0
12-12.
1
BX
A
CS10
OC
FOC
0
1
0
1
0
1
0
1
R/W
R/W
1
6
0
6
0
1
BW
B
Description
No clock source (Timer/Counter stopped).
clk
clk
clk
clk
clk
External clock source on T1 pin. Clock on falling edge.
External clock source on T1 pin. Clock on rising edge.
OC
I/O
I/O
I/O
I/O
I/O
R/W
R/W
1
5
–
0
5
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
BV
OC
R
1
R
4
–
0
4
0
BU
OC
R
R
1
3
–
0
3
0
AX
OC
1
R
R
2
–
0
2
0
AW
OC
R
1
R
1
–
0
1
0
AV
Figure 12-6 on page
ATtiny167
OC
R
1
R
0
–
0
0
0
AU
TCCR
TCCR
Figure
1
1
129
C
D