attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 102

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

11. Timer/Counter1 Prescaler
11.1
11.1.1
11.1.2
11.1.3
102
Overview
ATtiny167
Internal Clock Source
Prescaler Reset
External Clock Source
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
or f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the state
of the prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first
count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8,
64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T1 pin can be used as Timer/Counter clock (clk
T1 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector.
equivalent block diagram of the T1 synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (
high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 11-1. T1 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1 pin to the counter is updated.
CLK_I/O
/1024.
Tn
clk
I/O
CLK_I/O
D
LE
Q
). Alternatively, one of four taps from the prescaler can be used as a
Synchronization
D
Q
T1
pulse for each positive (CSn2:0 = 7) or negative
D
clk
CLK_I/O
I/O
Q
). The latch is transparent in the
Figure 11-1
Edge Detector
/8, f
CLK_I/O
shows a functional
Select Logic)
/64, f
(To Clock
Tn_sync
7728A–AUTO–07/08
CLK_I/O
T1
). The
/256,