attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 121

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

7728A–AUTO–07/08
the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B
interrupt flag will be set when a compare match occurs.
Figure 12-9. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When
either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set accord-
ingly at the same timer clock cycle as the OCR1A/B Registers are updated with the double
buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the
counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1A/B.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1A/B Registers are written. As the third period shown in
the TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCR1A/B
Register. Since the OCR1A/B update occurs at TOP, the PWM period starts and ends at TOP.
This implies that the length of the falling slope is determined by the previous TOP value, while
the length of the rising slope is determined by the new TOP value. When these two values differ
the two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1A/B1:0 to three (See
page
the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is gener-
ated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and
126). The actual OC1A/B value will only be visible on the port pin if the data direction for
TCNTn
OCnxi
OCnxi
Period
1
2
3
Figure 12-9
4
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
illustrates, changing
ATtiny167
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Table on
121