attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 188

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

17.6
188
Changing Channel or Reference Selection
ATtiny167
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 17-7. ADC Timing Diagram, Free Running Conversion
Table 17-1.
The MUX[4:0] and REFS[1:0] bits in the ADMUX register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and
reference selection only takes place at a safe point during the conversion. The channel and ref-
erence selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for the
ADC. Continuous updating resumes in the last ADC clock cycle before the conversion com-
pletes (ADIF in ADCSRA register is set). Note that the conversion starts on the following rising
ADC clock edge after ADSC is written. The user is thus advised not to write new channel or ref-
erence selection values to ADMUX until one ADC clock cycle after ADSC is written.
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Condition
First conversion
Normal conversions
Auto Triggered conversions
Conversion
Complete
Prescaler
Reset
One Conversion
11
12
ADC Conversion Time
MUX and REFS
Update
13
1
Next Conversion
1
Sign and MSB of Result
LSB of Result
2
2
MUX and REFS
Update
3
Sample &
Hold
3
4
Sample & Hold
(Cycles from Start of Conversion)
4
5
6
7
Sample & Hold
One Conversion
13.5 cycles
1.5 cycles
8
2 cycles
9
10
Conversion
Complete
11
12
13
Sign and MSB of Result
LSB of Result
Conversion Time (Cycles)
Next Conversion
1
Prescaler
Reset
2
13.5 cycles
25 cycles
13 cycles
7728A–AUTO–07/08