attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 130

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

12.11.5
12.11.6
12.11.7
12.11.8
130
ATtiny167
Timer/Counter1 – TCNT1H and TCNT1L
Output Compare Register A – OCR1AH and OCR1AL
Output Compare Register B – OCR1BH and OCR1BL
Input Capture Register – ICR1H and ICR1L
• Bit 3:0 – OC1Ai: Output Compare Pin Enable for Channel A
The OC1Ai bits enable the Output Compare pins of Channel A as shown in
116.
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers.
page 106.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a
compare match between TCNT1 and one of the OCR1A/B Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1A/B pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-
bit registers.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
See Section “12.3” on page 106.
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
OCR
OCR
4
0
4
0
4
0
4
0
TCNT
OCR
OCR
TCNT
ICR
ICR
1
1
1
1
1
1
1
A[15:8]
B[15:8]
1
[15:8]
A[7:0]
B[7:0]
[7:0]
[15:8]
[7:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
See Section “12.3” on
Figure 12-6 on page
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7728A–AUTO–07/08
TCNT
TCNT
OCR
OCR
OCR
OCR
ICR
ICR
1
1
1
1
1
1
H
L
1
1
AH
AL
BH
BL
H
L