attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 45

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

5.8.8
5.9
5.9.1
5.9.2
7728A–AUTO–07/08
Register Description
On-chip Debug System
SMCR – Sleep Mode Control Register
MCUCR – MCU Control Register
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
The Sleep Mode Control Register contains control bits for power management.
• Bits 7..3 Res: Reserved Bits
These bits are unused bits in the ATtiny167, and will always read as zero.
• Bits 2..1 – SM1..0: Sleep Mode Select Bits 1, and 0
These bits select between the four available sleep modes as shown in
Table 5-2.
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see
on page
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
SM1
0
0
1
1
41. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
Sleep Mode Select
R
7
–
0
R
7
–
0
SM0
0
1
0
1
BODS
R/W
6
0
R
6
–
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
BODSE
R/W
R
5
–
0
5
0
R
PUD
4
–
0
R/W
4
0
R
3
–
0
R
3
–
0
SM1
R/W
2
0
R
2
–
0
SM0
R/W
Table
1
0
R
1
–
0
ATtiny167
5-2.
R/W
SE
0
0
R
0
–
0
Table 5-1
MCUCR
SMCR
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