attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 71
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attiny167-esxz
Manufacturer Part Number
attiny167-esxz
Description
8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
Manufacturer
ATMEL Corporation
Datasheet
1.ATTINY167-ESXZ.pdf
(277 pages)
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7728A–AUTO–07/08
Table 9-2
Figure 9-6
internally in the modules having the alternate function.
Table 9-2.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
summarizes the function of the overriding signals. The pin and port indexes from
are not shown in the succeeding tables. The overriding signals are generated
Generic Description of Overriding Signals for Alternate Functions
Full Name
Pull-up Override
Enable
Pull-up Override
Value
Data Direction
Override Enable
Data Direction
Override Value
Port Value Override
Enable
Port Value Override
Value
Port Toggle Override
Enable
Digital Input Enable
Override Enable
Digital Input Enable
Override Value
Digital Input
Analog Input/Output
Description
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, (PUD or PDUx)} = 0, 1, 0.
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn, PUD
and PUDx Register bits.
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is enabled
by the DDxn Register bit.
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable is
determined by MCU state (Normal mode, sleep mode).
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV
is set/cleared, regardless of the MCU state (Normal mode, sleep
mode).
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but before
the synchronizer. Unless the Digital Input is used as a clock
source, the module with the alternate function will use its own
synchronizer.
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bi-
directionally.
ATtiny167
71
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