attiny167-esxz ATMEL Corporation, attiny167-esxz Datasheet - Page 11

• Manufacturer Part Number: attiny167-esxz
• Description: 8-bit Avr 8-bit Microcontroller Microcontroller With 16k Bytes In-system Programmable Flash And Lin Controller
• Manufacturer: ATMEL Corporation

2.6
2.7
7728A–AUTO–07/08
Instruction Execution Timing
Reset and Interrupt Handling
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 2-4
Harvard architecture and the fast access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per
cost, functions per clocks, and functions per power-unit.
Figure 2-4.
Figure 2-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 2-5.
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in
The list also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 – the External Inter-
rupt Request 0.
Register Operands Fetch
2nd Instruction Execute
3rd Instruction Execute
ALU Operation Execute
1st Instruction Execute
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
Total Execution Time
shows the internal timing concept for the Register File. In a single clock cycle an ALU
Result Write Back
shows the parallel instruction fetches and instruction executions enabled by the
The Parallel Instruction Fetches and Instruction Executions
Single Cycle ALU Operation
clk
clk
CPU
CPU
CPU
T1
T1
, directly generated from the selected clock source for the
T2
T2
Section 7. ”Interrupts” on page
T3
T3
ATtiny167
T4
T4
57.
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