ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 89
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
Table 32. Timer Control Register(TMR0_CTL = 0080h, TMR1_CTL = 0083h,
TMR2_CTL = 0086h, TMR3_CTL = 0089h, TMR4_CTL = 008Ch, or TMR5_CTL =
008Fh)
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
PRT_IRQ
6
IRQ_EN
5
4
PRT_MODE
[3:2]
CLK_DIV
1
RST_EN
0
PRT_EN
Value
0
1
0
1
0
0
1
00
01
10
11
0
1
0
1
Description
The timer does not reach its end-of-count value. This bit is reset
to 0 every time the TMRx_CTL register is read.
The timer reaches its end-of-count value. If IRQ_EN is set to 1,
an interrupt signal is sent to the CPU. This bit remains 1 until the
TMRx_CTL register is read.
Timer interrupt requests are disabled.
Timer interrupt requests are enabled.
Reserved.
The timer operates in SINGLE PASS mode. PRT_EN (bit 0) is
reset to 0, and counting stops when the end-of-count value is
reached.
The timer operates in CONTINUOUS mode. The timer reload
value is written to the counter when the end-of-count value is
reached.
Clock ÷ 4 is the timer input source.
Clock ÷ 16 is the timer input source.
Clock ÷ 64 is the timer input source.
Clock ÷ 256 is the timer input source.
The reload and restart function is disabled.
The reload and restart function is enabled. When a 1 is written to
this bit, the values in the reload registers are loaded into the
downcounter when the timer restarts. The programmer must
ensure that this bit is set to 1 each time SINGLE-PASS mode is
used.
The programmable reload timer is disabled.
The programmable reload timer is enabled.
R
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
Programmable Reload Timers
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
82
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