ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 46

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

General-Purpose Input/Output
Table 6. GPIO Mode Selection
PS015313-0508
GPIO
Mode
1
GPIO Overview
GPIO Operation
Px_ALT2
Bits7:0
0
0
The eZ80F92 device features 24 General-Purpose Input/Output (GPIO) pins. The GPIO
pins are assembled as three 8-bit ports—Port B, Port C, and Port D. All port signals can be
configured for use as either inputs or outputs. In addition, all of the port pins can be used
as vectored interrupt sources for the CPU.
The GPIO operation is the same for all three GPIO ports (Ports B, C, and D). Each port
features eight GPIO port pins. The operating mode for each pin is controlled by four bits
that are divided between four 8-bit registers.
These GPIO mode control registers are:
•
•
•
•
where x can be B, C, or D representing any of the three GPIO ports B, C, or D. The mode
for each pin is controlled by setting each register bit pertinent to the pin to be configured.
For example, the operating mode for Port B Pin 7 (PB7), is set by the values contained in
PB_DR[7], PB_DDR[7], PB_ALT1[7], and PB_ALT2[7].
The combination of the GPIO control register bits allows individual configuration of each
port pin for nine modes. In all modes, reading of the Port x Data register returns the sam-
pled state, or level, of the signal on the corresponding pin.
each port signal based upon these four register bits. After a RESET event, all GPIO port
pins are configured as standard digital inputs, with interrupts disabled.
Port x Data Register (Px_DR)
Port x Data Direction Register (Px_DDR)
Port x Alternate Register 1 (Px_ALT1)
Port x Alternate Register 2 (Px_ALT2)
Px_ALT1
Bits7:0
0
0
Px_DDR
Bits7:0
0
0
Px_DR
Bits7:0 Port Mode
0
1
Output
Output
Table 6
General-Purpose Input/Output
Product Specification
lists the function of
eZ80F92/eZ80F93
Output
0
1
39