ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 50

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
GPIO Control Registers
an interrupt request signal to the CPU. Any time a port pin is configured for edge-trig-
gered interrupt, writing a 1 to that pin’s Port x Data register causes a reset of the edge-
detected interrupt. The programmer must set the bit in the Port x Data register to 1 before
entering either single or dual edge-triggered interrupt mode for that port pin.
When configured for dual edge-triggered interrupt mode (GPIO Mode 6), both a rising
and a falling edge on the pin cause an interrupt request to be sent to the CPU.
When configured for single edge-triggered interrupt mode (GPIO Mode 9), the value in
the Port x Data register determines if a positive or negative edge causes an interrupt
request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges.
The 12 GPIO Control Registers operate in groups of four with a set for each Port (B, C,
and D). Each GPIO port features a Port Data register, Port Data Direction register, Port
Alternate register 1, and Port Alternate register 2.
Port x Data Registers
When the port pins are configured for one of the output modes, the data written to the
Port x Data registers, listed in
reading from the Port x Data registers always returns the current sampled value of the cor-
responding pins.
When the port pins are configured as edge-triggered interrupt sources, writing a 1 to the
corresponding bit in the Port x Data register clears the interrupt signal that is sent to the
CPU. When the port pins are configured for edge-selectable interrupts or level-sensitive
interrupts, the value written to the Port x Data register bit selects the interrupt edge or
interrupt level. See
Table 7. Port x Data Registers; (PB_DR = 009Ah, PC_DR = 009Eh, PD_DR = 00A2h)
Bit
Reset
CPU Access
Note: X = Undefined; R/W = Read/Write.
Table 6
R/W
on page 39 for more information.
X
7
Table
R/W
X
7, are driven on the corresponding pins. In all modes,
6
R/W
X
5
R/W
X
4
R/W
X
3
General-Purpose Input/Output
Product Specification
R/W
X
2
eZ80F92/eZ80F93
R/W
X
1
R/W
X
0
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