ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 186
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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PS015313-0508
ZDI Bus Control Register
The ZDI Bus Control register controls bus requests during DEBUG mode. It enables or
disables bus acknowledge in ZDI DEBUG mode and allows ZDI to force assertion of the
BUSACK signal. This register should only be written during ZDI DEBUG mode (that is,
following a BREAK). See
Table 100. ZDI Bus Control Register(ZDI_BUS_CTL = 17h in the ZDI Register Write
Only Address Space)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit Position
7
ZDI_BUSAK_EN
6
ZDI_BUSAK
[5:0]
Value
0
1
0
1
000000
Table
W
7
0
100.
Description
Bus requests by external peripherals using the BUSREQ
pin are ignored. The bus acknowledge signal, BUSACK,
is not asserted in response to any bus requests.
Bus requests by external peripherals using the BUSREQ
pin are accepted. A bus acknowledge occurs at the end
of the current ZDI operation. The bus acknowledge is
indicated by asserting the BUSACK pin in response to a
bus request.
Deassert the bus acknowledge pin (BUSACK) to return
control of the address and data buses back to ZDI.
Assert the bus acknowledge pin (BUSACK) to pass
control of the address and data buses to an external
peripheral.
Reserved.
W
6
0
W
5
0
W
4
0
W
3
0
Product Specification
W
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
W
1
0
W
0
0
179
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