ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 118

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
UART Registers
Table 53. UART Baud Rate Generator Register—High Bytes(UART0_BRG_H =
After a RESET, all UART registers are set to their default values. Any writes to unused
registers or register bits are ignored and reads return a value of 0. For compatibility with
future revisions, unused bits within a register should always be written with a value of 0.
Read/Write attributes, reset conditions, and bit descriptions of all of the UART registers
are provided in this section.
UART Transmit Holding Register
If less than eight bits are programmed for transmission, the lower bits of the byte written
to this register are selected for transmission. The transmit FIFO is mapped at this address.
The user can write up to 16 bytes for transmission at one time to this address if the FIFO is
enabled by the application. If the FIFO is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_RBR and UARTx_BRG_L
registers. See
00C1h, UART1_BRG_H = 00D1h)
Bit
Position
[7:0]
UART_BRG_L
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
[7:0]
UART_BRG_H
Table 54
Value
00h–
FFh
Value
00h–
FFh
on page 112.
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
7
0
R/W
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80F92/eZ80F93
R/W
1
0
R/W
0
0
111