ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 48

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Note:
GPIO Mode 5—
GPIO Mode 6—
falling edge on the pin cause an interrupt request to be sent to the CPU. Writing a 1 to the
Port x Data register bit position resets the corresponding interrupt request. Writing a 0 pro-
duces no effect. The programmer must set the Port x Data register before entering the
edge-triggered interrupt mode.
GPIO Mode 7—
the alternate (secondary) functions assigned to the pin. For example, the alternate mode
function for PC7 is RI1 and the alternate mode function for PB4 is the Timer 4 Out. When
GPIO Mode 7 is enabled, the pin output data and pin tristated control come from the alter-
nate function's data output and tristate control, respectively. The value in the Port x Data
register produces no effect on operation.
GPIO Mode 8—
rupt request is generated when the level at the pin is the same as the level stored in the Port
x Data register. The port pin value is sampled by the system clock. The input pin must be
held at the selected interrupt level for a minimum of 2 clock periods to initiate an interrupt.
The interrupt request remains active as long as this condition is maintained at the external
source.
GPIO Mode 9—
value in the Port x Data register determines if a positive or negative edge causes an inter-
rupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. The interrupt request remains active until a 1 is writ-
ten to the corresponding interrupt request of the Port x Data register bit. Writing a 0 pro-
duces no effect on operation. The programmer must set the Port x Data register before
entering the edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is displayed in
Input signals are sampled by the system clock before being passed to the alternate
function input.
Reserved. This pin produces high-impedance output.
This bit enables a dual edge-triggered interrupt mode. Both a rising and a
For Ports B, C, and D, the port pin is configured to pass control over to
The port pin is configured for level-sensitive interrupt modes. An inter-
The port pin is configured for single edge-triggered interrupt mode. The
Figure 5
General-Purpose Input/Output
Product Specification
eZ80F92/eZ80F93
on page 42.
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