ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 122

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Table 58. UART Interrupt Status Codes (Continued)
UART FIFO Control Register
This register is used to monitor trigger levels, clear FIFO pointers, and enable or disable
the FIFO. The UARTx_FCTL registers share the same I/O addresses as the UARTx_IIR
registers. See
Table 59. UART FIFO Control Registers(UART0_FCTL = 00C2h, UART1_FCTL =
00D2h)
INSTS
Value
001
000
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:6]
TRIG
[5:3]
2
CLRTXF
Table
Priority
Fifth
Lowest
Value
00
01
10
11
000
0
1
59.
Description
Receive FIFO trigger level set to 1. Receive data interrupt is
generated when there is 1 byte in the FIFO. Valid only if FIFO
is enabled.
Receive FIFO trigger level set to 4. Receive data interrupt is
generated when there are 4 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 8. Receive data interrupt is
generated when there are 8 bytes in the FIFO. Valid only if
FIFO is enabled.
Receive FIFO trigger level set to 14. Receive data interrupt is
generated when there are 14 bytes in the FIFO. Valid only if
FIFO is enabled.
Reserved.
No effect.
Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
W
Interrupt Type
Transmit Buffer Empty
Modem Status
7
0
W
6
0
W
5
0
Universal Asynchronous Receiver/Transmitter
W
4
0
W
3
0
Product Specification
W
2
0
eZ80F92/eZ80F93
W
1
0
W
0
0
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