ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 49

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
GPIO Interrupts
Each port pin can be used as an interrupt source. Interrupts can be either level- or edge-
triggered.
Level-Triggered Interrupts
When the port is configured for level-triggered interrupts, the corresponding port pin is
tristated. An interrupt request is generated when the level at the pin is the same as the level
stored in the Port x Data register. The port pin value is sampled by the system clock. The
input pin must be held at the selected interrupt level for a minimum of 2 consecutive clock
cycles to initiate an interrupt. The interrupt request remains active as long as this condition
is maintained at the external source.
For example, if PD3 is programmed for low-level interrupt and the pin is forced Low for 2
consecutive clock cycles, an interrupt request signal is generated from that port pin and
sent to the CPU. The interrupt request signal remains active until the external device
driving PD3 forces the pin High.
Edge-Triggered Interrupts
When the port is configured for edge-triggered interrupts, the corresponding port pin is
tristated. If the pin receives the correct edge from an external device, the port pin generates
System Clock
Data Bus
GPIO Register
Data (Output)
D
System Clock
Figure 5. GPIO Port Pin Block Diagram
Q
Mode 1
Mode 4
Mode 1
Mode 3
GPIO Register
Data (Input)
Q
D
Q
General-Purpose Input/Output
Product Specification
D
GND
eZ80F92/eZ80F93
V
DD
Port
Pin
42