ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 199

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
RAM Control Registers
RAM Control Register
The internal data RAM can be disabled by clearing the RAM_EN bit. The default, upon
RESET, is for RAM to be enabled.
Table 111. RAM Control Register; (RAM_CTL = 00B4h)
RAM Address Upper Byte Register
The RAM_ADDR_U register defines the upper byte of the address for the on-chip RAM.
If enabled, RAM addresses assume priority over all Chip Selects. The external Chip Select
signals are not asserted if the corresponding RAM address is enabled.
Table 112. RAM Address Upper Byte Register; (RAM_ADDR_U = 00B5h)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
RAM_EN
[6:0]
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
RAM_ADDR_U
Value
0
1
0000000 Reserved
Value Description
00h–
FFh
R/W
R/W
This byte defines the upper byte of the RAM address. On-chip
RAM is prioritized over all Memory Chip Selects. If the enabled
RAM and Chip Select addresses overlap, the external Chip
Select is not asserted.
7
1
7
1
Description
On-chip general-purpose RAM is disabled
On-chip general-purpose RAM is enabled
R/W
R
6
0
6
1
R/W
R
5
0
5
1
R/W
R
4
0
4
1
R/W
R
3
0
3
1
Product Specification
Random Access Memory
R/W
R
2
0
2
1
eZ80F92/eZ80F93
R/W
R
1
0
1
1
R/W
R
0
0
0
1
192