ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 246

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ez80f92

Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet

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Table 153. Bus Acknowledge Timing
Table 154. PHI System Clock Timing
PS015313-0508
External Bus Acknowledge Timing
External System Clock Driver (PHI) Timing
Table 153
ter detects BUSACK asserted and drives IORQN, MREQN, A[23:0] there is an asynchro-
nous prop delay to the CS[3:0] outputs being valid.
Table 154
als to synchronize with the internal system clock driver on the eZ80F92 device.
Parameter
T
T
T
Parameter
T
T
1
2
3
1
2
lists information about the bus acknowledge timing. Once the external bus mas-
lists timing information for the PHI pin. The PHI pin allows external peripher-
Abbreviation
Clock Rise to BUSACK Assertion Delay
Clock Rise to BUSACK Deassertion Delay
IORQN, MREQN, A[23:0] input to CS[3:0]
output prop delay
Abbreviation
Clock (XIN) Rise to PHI Rise
Clock (XIN) Fall to PHI Fall
Product Specification
Min
Min
Electrical Characteristics
2.0
2.0
Delay (ns)
Delay (ns)
Max
14.0
14.0
10.0
Max
6.0
6.0
238

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