ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 129

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Table 65. UART Modem Status Registers(UART0_MSR = 00C6h, UART1_MSR =
00 D6h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
DCD
6
RI
5
DSR
4
CTS
3
DDCD
2
TERI
1
DDSR
0
DCTS
Value
0–1
0–1
0–1
0–1
0–1
0–1
0–1
0–1
Description
Data Carrier Detect
In NORMAL mode, this bit reflects the inverted state of the
DCDx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[3] = out2.
Ring Indicator
In NORMAL mode, this bit reflects the inverted state of the RIx
input pin. In LOOP BACK mode, this bit reflects the value of the
UARTx_MCTL[2] = out1.
Data Set Ready
In NORMAL mode, this bit reflects the inverted state of the
DSRx input pin. In LOOP BACK mode, this bit reflects the
value of the UARTx_MCTL[0] = DTR.
Clear To Send
In NORMAL mode, this bit reflects the inverted state of the
CTSx input pin. In LOOP BACK mode, this bit reflects the value
of the UARTx_MCTL[1] = RTS.
Delta Status Change of DCD
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS
This bit is set to 1 whenever the CTSx pin changes state.
This bit is reset to 0 when the UARTx_MSR register is read.
X
R
7
X
R
6
R
X
5
Universal Asynchronous Receiver/Transmitter
R
X
4
R
X
3
Product Specification
R
X
2
eZ80F92/eZ80F93
X
R
1
X
R
0
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