ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 159

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Note:
is transmitted, the IFLG is set and the I2C_SR register contains
the idle state. The AAK bit must be set to 1 before reentering SLAVE mode.
If no acknowledge is received after transmitting a byte, the IFLG is set and the I2C_SR
register contains
If a STOP condition is detected after an acknowledge bit, the I
Slave Receive
In SLAVE RECEIVE mode, a number of data bytes are received from a master transmit-
ter.
The I
Write bit (lsb = 0) after a START condition. The I
sets the IFLG bit in the I2C_CTL register and the I2C_SR register contains the status code
60h
address
I
the transmission of an address, and the slave address and Write bit (or the general call
address if the CGE bit in the I2C_SAR register is set to 1) are received. The status code in
the I2C_SR register is
address is received. The IFLG bit must be cleared to 0 to allow data transfer to continue.
If the AAK bit in the I2C_CTL register is set to 1 then an acknowledge bit (Low level on
SDA) is transmitted and the IFLG bit is set after each byte is received. The I2C_SR regis-
ter contains the status code
general call address. The received data byte can be read from the I2C_DR register and the
IFLG bit must be cleared to allow the transfer to continue. If a STOP condition or a
repeated START condition is detected after the acknowledge bit, the IFLG bit is set and
the I2C_SR register contains status code
If the AAK bit is cleared to 0 during a transfer, the I
(High level on SDA) after the next byte is received, and set the IFLG bit. The I2C_SR reg-
ister contains the status code
general call address. The I
2
C goes from MASTER mode to SLAVE RECEIVE mode when arbitration is lost during
. The I
2
C enters SLAVE RECEIVE mode when it receives its own slave address and a
00h
When the I
I2C_SAR register), it transmits an acknowledge after the first address byte is
received but no interrupt is generated. IFLG is not set and the status does not
change. The I
received. The I
2
C also enters SLAVE RECEIVE mode when it receives the general call
(if the GCE bit in the I2C_SAR register is set). The status code is then
C0h
2
. The I
C contains a 10-bit slave address (signified by
68h
2
2
C generates an interrupt only after the second address byte is
C sets the IFLG bit and loads the status code as described above.
2
C returns to the idle state when the IFLG bit is cleared to 0.
if the slave address is received or
80h
2
C then returns to the idle state.
88h
or
or
90h
98h
if SLAVE RECEIVE mode is entered with the
A0h
if SLAVE RECEIVE mode is entered with the
.
2
C transmits an acknowledge bit and
2
C transmits a not-acknowledge bit
78h
2
C returns to the idle state.
C8h
Product Specification
if the general call
and the I
I2C Serial I/O Interface
F0h
2
–
C returns to
F7h
70h
in the
.
152