ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 127

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
UART Line Status Register
This register is used to show the status of UART interrupts and registers. See
Table 64. UART Line Status Registers(UART0_LSR = 00C5h, UART1_LSR = 00 D5h)
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
7
ERR
6
TEMT
5
THRE
4
BI
Value
0
1
0
1
0
1
0
1
Description
Always 0 when operating in with the FIFO disabled. With the
FIFO enabled, this bit is reset when the UARTx_LSR register is
read and there are no more bytes with error status in the FIFO.
Error detected in the FIFO. There is at least 1 parity, framing or
break indication error in the FIFO.
Transmit holding register/FIFO is not empty or transmit shift
register is not empty or transmitter is not idle.
Transmit holding register/FIFO and transmit shift register are
empty; and the transmitter is idle. This bit cannot be set to 1
during the BREAK condition. This bit only becomes 1 after the
BREAK command is removed.
Transmit holding register/FIFO is not empty.
Transmit holding register/FIFO is empty. This bit cannot be set
to 1 during the BREAK condition. This bit only becomes 1 after
the BREAK command is removed.
Receiver does not detect a BREAK condition. This bit is reset
to 0 when the UARTx_LSR register is read.
Receiver detects a BREAK condition on the receive input line.
This bit is 1 if the duration of BREAK condition on the receive
data is longer than one character transmission time, the time
depends on the programming of the UARTx_LSR register. In
case of FIFO only one null character is loaded into the receiver
FIFO with the framing error. The framing error is revealed to
the CPU whenever that particular data is read from the receiver
FIFO.
R
7
0
R
6
1
R
5
1
Universal Asynchronous Receiver/Transmitter
R
4
0
R
3
0
Product Specification
R
2
0
eZ80F92/eZ80F93
R
1
0
Table
64.
R
0
0
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