ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 39
ez80f92
Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet
1.EZ80F92.pdf
(261 pages)
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Reset
PS015313-0508
Reset Operation
Power-On Reset
Note:
The Reset controller within the eZ80F92 device provides a consistent reset function for all
types of resets that can affect the system. A system reset, referred in this document as
RESET, returns the eZ80F92 device to a defined state. All internal registers affected by
RESET return to their default conditions. RESET configures the GPIO port pins as inputs
and clears the CPU’s Program Counter to
during RESET.
The events that can cause a RESET are:
•
•
•
•
•
•
During a RESET, an internal RESET mode timer holds the system in RESET mode for
257 system clock (SCLK) cycles. The RESET mode timer begins incrementing on the
next rising edge of SCLK following deactivation of all RESET events.
A Power-On Reset (POR) occurs each time the supply voltage to the part rises from below
the Voltage Brownout threshold to above the POR voltage threshold (V
bandgap-referenced voltage detector sends a continuous RESET signal to the Reset con-
troller until the supply voltage (V
above V
Reset controller (T
until the RESET mode timer expires. POR operation is displayed in
The signals in this figure are not drawn to scale and are for displaying purposes only.
Power-On Reset (POR)
Low-Voltage Brownout (VBO)
External RESET pin assertion
Watchdog Timer (WDT) time-out when configured to generate a RESET
Real-Time Clock alarm with the CPU in low-power SLEEP mode
Execution of a debug reset command
You must determine if 257 SCLK cycles provides sufficient time for the primary
crystal oscillator to stabilize.
POR
, an on-chip analog delay element briefly maintains the RESET signal to the
ANA
). After this analog delay, the eZ80F92 device is in RESET mode
CC
) exceeds the POR voltage threshold. After V
000000h
. Program code execution ceases
Product Specification
Figure 3
POR
). The internal
on page 33.
CC
Reset
rises
32
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