ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 133

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
UART
Baud Rate
IR
8-clock
delay
Clock
RxD
RxD
The UART baud rate clock is used by the IrDA endec to generate the demodulated signal
(RxD) that drives the UART. Each UART bit period is sixteen baud-clocks wide. Each
IR_RXD bit is encoded during a bit period such that a 0 is represented by a pulse and a 1 is
represented by no pulse. The IrDA Physical Layer Specification describes a nominal pulse
as being
(Low), a 3-clock-wide Low (0) pulse is received following a 7-clock High (1) period.
Following the 3-clock Low pulse is a 6-clock High pulse to complete the full 16-clock
data period. If the data to be received is a logical 1 (High), the IR_RxD signal is held High
(1) for the full 16-clock period. Data reception is displayed in
The IrDA Physical Layer Specification allows for a minimum signal width as well as the
nominal signal width described above. By definition, the received pulse duration can be as
small as 1.41 seconds for all baud rates up to 115.2 kbps.
and maximum pulse durations for all baud rates supported by the eZ80
frequency divider based upon the system clock frequency measures this time limit and
allows legal signals to pass to UART0.
Table 67. IrDA Physical Layer 1.4 Pulse Durations Specifications
Baud Rate
Start Bit = 0
16-clock
19200
38400
period
9600
3
/
1.4 s
min. pulse
16
of a bit period wide. In this case, if the data to be received is a logical 0
16-clock
period
Figure 28.Infrared Data Reception
Data Bit 0 = 1
Minimum Pulse
Width
1.41 s
1.41 s
1.41 s
16-clock
period
Data Bit 1 = 0
Maximum Pulse
16-clock
period
22.13 s
11.07 s
Width
5.96 s
Data Bit 2 = 1
Table 67
Figure
16-clock
period
Product Specification
Infrared Encoder/Decoder
outlines the minimum
Data Bit 3 = 1
28.
®
CPU. A receiver
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