ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 161

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Table 84. I
I
The I2C_XSAR register is used in conjunction with the I2C_SAR register to provide
10-bit addressing of the I
8 bits of the 10-bit slave address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}.
When the register receives an address starting with
the I
after receiving the I2C_XSAR byte (the device does not generate an interrupt at this
point). After the next byte of the address (I2C_XSAR) is received, the I
interrupt and goes into SLAVE mode. Then I2C_SAR[2:1] are used as the upper 2 bits for
the 10-bit extended address. The full 10-bit address is supplied by {I2C_SAR[2:1],
I2C_XSAR[7:0]}. See
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:1]
SLA
0
GCE
2
C Extended Slave Address Register
2
C recognizes that a 10-bit slave addressing mode is selected. The I
2
C Slave Address Registers(I2C_SAR = 00C8h)
Value Description
00h–
7Fh
0
1
Table 85
2
C when in SLAVE mode. The I2C_SAR value forms the lower
R/W
7-bit slave address or upper 2 bits,I2C_SAR[2:1], of address
when operating in 10-bit mode.
I
I
7
0
2
2
C not enabled to recognize the General Call Address.
C enabled to recognize the General Call Address.
on page 155.
R/W
6
0
R/W
5
0
R/W
F7h
4
0
to
F0h
R/W
3
0
(I2C_SAR[7:3] = 11110b),
Product Specification
R/W
2
0
I2C Serial I/O Interface
2
2
C generates an
C sends an ACK
R/W
1
0
R/W
0
0
154