ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 44

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ez80f92

Manufacturer Part Number
ez80f92
Description
Ez80acclaim Flash Microcontrollers
Manufacturer
ZiLOG Semiconductor
Datasheet

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PS015313-0508
Table 4. Clock Peripheral Power-Down Register; (CLK_PPD1 = 00DBh)
Bit
Reset
CPU Access
Note: R/W = Read/Write; R = Read Only.
Bit
Position
7
GPIO_D_OFF
6
GPIO_C_OFF
5
GPIO_B_OFF
4
3
SPI_OFF
2
I2C_OFF
1
UART1_OFF
0
UART0_OFF
Value Description
1
0
1
0
1
0
1
0
1
0
1
0
1
0
System clock to GPIO Port D is powered down.
Port D alternate functions do not operate correctly.
System clock to GPIO Port D is powered up.
System clock to GPIO Port C is powered down.
Port C alternate functions do not operate correctly.
System clock to GPIO Port C is powered up.
System clock to GPIO Port B is powered down.
Port B alternate functions do not operate correctly.
System clock to GPIO Port B is powered up.
Reserved.
System clock to SPI is powered down.
System clock to SPI is powered up.
System clock to I
System clock to I
System clock to UART1 is powered down.
System clock to UART1 is powered up.
System clock to UART0 and IrDA endec is powered down.
System clock to UART0 and IrDA endec is powered up.
R/W
7
0
R/W
6
0
R/W
2
2
5
0
C is powered down.
C is powered up.
R
4
0
R/W
3
0
Product Specification
R/W
2
0
Low-Power Modes
R/W
1
0
R/W
0
0
37

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