ez80f92 ZiLOG Semiconductor, ez80f92 Datasheet - Page 156

• Manufacturer Part Number: ez80f92
• Description: Ez80acclaim Flash Microcontrollers
• Manufacturer: ZiLOG Semiconductor

PS015313-0508
Table 80. I
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit in the
I2C_CTL register. The I
to the idle state.
Master Receive
In MASTER RECEIVE mode, the I
ter.
After the START condition is transmitted, the IFLG bit is 1 and the status code
loaded in the I2C_SR register. The I2C_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a Read.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
I2C_SR register.
Table 81. I
Code I
30h
38h
Code
40h
R = Read bit; that is, the lsb is set to 1.
Data byte transmitted,
ACK not received
Arbitration lost
2
C State
2
2
I
Addr + R
transmitted, ACK
received
C Master Transmit Status Codes For Data Bytes (Continued)
C Master Receive Status Codes
2
C State
2
C then transmits a STOP condition, clears the STP bit and returns
Microcontroller Response Next I
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
Microcontroller Response Next I
For a 7-bit address,
clear IFLG, AAK = 0
Or clear IFLG, AAK = 1
For a 10-bit address
Write extended address
byte to DATA, clear IFLG
2
C receives a number of bytes from a slave transmit-
Same as code 28h
Return to idle
Transmit START when bus
free
Receive data byte,
transmit NACK
Receive data byte,
transmit ACK
Transmit extended
address byte
Product Specification
2
Table 81
C Action
I2C Serial I/O Interface
2
C Action
is in the
08h
is
149